The capacitance and/or frequency of a varactor or Variable Voltage Capacitor varies directly as the applied voltage varies, and consequently finds significant application with oscillator circuits such as used in communication devices. As an example, an oscillator circuit that is controlled by a varactor offers high-speed operation, low noise and low power consumption. The operating frequency of such an oscillator can be controlled or tuned by varying the voltage across the terminals of the varactor and, therefore, ideally the varactor will have a high maximum to minimum capacitance ratio. This is because the difference between the maximum and minimum capacitance over the full range of the controlled voltage will be proportional to the tuning range of the oscillator. Thus, a large capacitance range results in a large tuning range of the oscillator. The ideal variable voltage capacitor will also operate substantially linearly over a large voltage range such that the oscillator changes its operating frequency smoothly over a large voltage range.
FIG. 1A illustrates the circuit schematic of an ideal LC oscillator (inductive capacitance) voltage controlled variable circuit or varactor, and FIG. 1B illustrates a linear relationship between the applied voltage Vc (on the horizontal axis 10) and the operating frequency Hz of the oscillator (on the vertical axis 12). Unfortunately, as will be appreciated by those skilled in the art, semiconductor varactors or Variable Voltage Capacitors, simply do not demonstrate such a linear relationship.
Prior art semiconductor varactors are primarily of two types: a PN-junction varactor and a MOS varactor. The PN-junction varactor has the advantage that it can be implemented in a standard CMOS semiconductor process. Unfortunately, the PN-junction has a low maximum to minimum capacitance ratio, which, of course, as discussed above limits the operating frequency range of an oscillator using such a PN-junction varactor. On the other hand, a MOS varactor, such as shown in the semiconductor structure diagram of FIG. 2A and the electrical schematic of the back-to-back pair of varactors shown in FIG. 2B has an acceptable capacitance ratio, but the transition from the minimum C1 to the maximum C2 as shown in the graph of FIG. 2C from maximum to minimum or minimum to maximum, and as will be discussed later, is very abrupt over a small gate voltage (Vg) range V1, V2 such that the device is very non-linear.
One attempt to achieve the goal is described in U.S. Pat. No. 6,407,412 entitled “MOS Varactor Structure with Engineered Voltage Control Range” and issued to Krzysztof Iniewski, et al. on Jun. 18, 2002. However, the device requires a somewhat complicated process flow to provide the necessary P+ and N+ parallel-connected regions.
Therefore, it would be advantageous to provide a semiconductor varactor having a large capacitance ratio, which varies linearly over a large input voltage and can be manufactured by using standard CMOS processing.